Formal Verification Technical lead
Description
In this role you will be responsible for developing mathematical proofs using model checking tools, to find RTL (Verilog) bugs or prove their absence.
Requirements
- 5+ years of experience in Formal Verification
- B.Sc. in Mathematics and Computer Science, Electrical/Computer Engineering, M.Sc/PhD Mathematics
- Strong debug skills
- In-depth knowledge of how Formal works
- Experience in System Verilog - Advantage
- Knowledge in Industry Standard protocols such as AXI/AHB/APB/CHI - Advantage
Responsibilities
- You will verify unique and complex design blocks
- Help determine the Formal strategy and methodology for the team
- Explore new Formal methods and Tools
NextSilicon is proud to be an Equal Opportunity Employer. We do not discriminate based upon race, religion, color, age, national origin, gender (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, genetic information, status as a protected veteran, status as an individual with physical or mental disability, or other applicable legally protected characteristics. This policy applies to all employment practices within our organization, including hiring, recruiting, promotion, termination, layoff, recall, leave of absence, compensation, benefits, training, and apprenticeship. NextSilicon makes hiring decisions based solely on qualifications, merit, and business needs at the time.
