India- Physical Design Manager

NextSilicon is reimagining high-performance computing. Our accelerated compute solutions leverage intelligent adaptive algorithms to vastly accelerate supercomputers, driving them forward into a new generation. Our new software-defined hardware architecture enables HPC to fulfill its promise of breakthroughs in all fields of advanced research. 

At NextSilicon, everything we do is guided by three core values:

• Professionalism: We strive for exceptional results through professionalism and unwavering dedication to quality and performance. 
• Unity: Collaboration is key to success. That's why we foster a work environment where every employee can feel valued and heard. 
• Impact: We're passionate about developing technologies that make a meaningful impact on industries, communities, and individuals worldwide.

At NextSilicon, we are reimagining high-performance computing. Our pioneering coprocessor vastly accelerates supercomputers, driving them forward into a new generation. Our new software-defined hardware architecture enables HPC to fulfill its promise of breakthroughs in all fields of advanced research.

NextSilicon is looking for a talented and experienced manager to play a crucial role in the physical design implementation of the company’s next SOC. The Physical Design Manager leads a team of engineers responsible for the physical implementation of high-performance digital and mixed-signal ASICs or SoCs. This role ensures that the chip layout is optimized for performance, power, and area while meeting stringent timing and physical constraints. The Physical Design Manager collaborates closely with RTL designers, verification teams, and other cross-functional groups to deliver high-quality designs that meet both functional and physical specifications.

• 15+ years of physical design experience, leading complex process designs
• In-depth knowledge of process and circuit design
• Knowledge of physical design industry standards and practices, including physically aware synthesis, floor planning, CTS, place and route, clock tree synthesis (CTS), timing closure and signoff
• Experience in developing and implementing power-grid and clock specifications
• Have good command of industry-standard physical design and synthesis tools
• Understanding of scripting languages, such as Perl and Tcl
• Working knowledge of extraction and STA methodologies and tools
• Good understanding of physical design verification methodology for debugging LVS and DRC issues at chip and block level
• Proficiency in power delivery, signal integrity, advanced packaging, power projection, and design for low dynamic power
• Leading projects and managing small groups: advantage

• Lead, coach and manage a team of physical designer throughout the IC design process
• Oversee project schedules, ensuring timely delivery of milestones within budget.
• Generate and analyze critical block- and chip-level static timing constraints
• Spec and define full chip floor plan, including pin placement, partitions, and power grid
• Develop and validate high-performance, low-power clock network guidelines
• Perform critical block-level place and route and create designs that meet timing, area, and power constraints
• Review the vendors’ physical design verification flow at chip and block level and guide other designers on how to fix LVS and DRC violations
• Work with vendors on defining physical design methodologies and assist in flow development for chip
• Manage design rule checking (DRC), layout versus schematic (LVS) checks, and timing analysis.
• Prepare reports, design documentation, and project status updates for internal teams and stakeholders.
• Track and document design iterations, improvements, and lessons learned for future projects.