India-Senior Physical Design Engineer

NextSilicon is reimagining high-performance computing. Our accelerated compute solutions leverage intelligent adaptive algorithms to vastly accelerate supercomputers, driving them forward into a new generation. Our new software-defined hardware architecture enables HPC to fulfill its promise of breakthroughs in all fields of advanced research. 

At NextSilicon, everything we do is guided by three core values:

• Professionalism: We strive for exceptional results through professionalism and unwavering dedication to quality and performance. 
• Unity: Collaboration is key to success. That's why we foster a work environment where every employee can feel valued and heard. 
• Impact: We're passionate about developing technologies that make a meaningful impact on industries, communities, and individuals worldwide.

At NextSilicon, we are reimagining high-performance computing. Our pioneering coprocessor vastly accelerates supercomputers, driving them forward into a new generation. Our new software-defined hardware architecture enables HPC to fulfill its promise of breakthroughs in all fields of advanced research.

NextSilicon is looking for a talented and experienced engineer to participate in the physical design of the company’s product for leading one of Nextsilison BE projects. This position involves working with external back-end developers as well as carrying out critical tasks in-house, and leading aggressive back-end initiatives to meet challenging targets in terms of area, timing, and layout. In this role, you will be at the center of the company’s design efforts and will have a significant influence on product architecture.

• 4 to 10 years of experience in physical design for semiconductor devices, with proven expertise in IC physical design flow
• Hands-on experience with EDA tools like Synopsys ICC2, Cadence Innovus, and Mentor Calibre.
• Strong knowledge of STA, floorplanning, placement, routing, and clocking methodologies.
• Proficient in power analysis and power management techniques.
• Familiar with scripting languages such as Python, Perl, or Tcl for automation.
• Good understanding of process technologies and design rules.
• Excellent problem-solving skills and attention to detail.
• Ability to work in a fast-paced environment and meet deadlines.
• Strong communication skills for effective collaboration with cross-functional teams.

• Perform synthesis, floorplanning, placement, clock tree synthesis (CTS), and routing of IC designs at block and Sub-system level
• Convert high-level RTL (Register Transfer Level) code into a manufacturable silicon layout while meeting PPA goals, both at Block and Sub-system level
• Conduct static timing analysis (STA) and optimize for timing closure across various corners.
• Analyze and resolve issues related to power distribution, signal integrity, and noise
• Ensure designs meet all design rules and verify the physical layout against the logical schematic. Be able to resolve all DRC and LVS issue in their designs
• Optimize power consumption through techniques like power gating, voltage scaling, and clock gating.
• Manage dynamic and static power consumption to meet design specifications.
• Utilize EDA (Electronic Design Automation) tools such as Cadence, Synopsys, and Mentor Graphics for design implementation.
• Work closely with RTL design, verification, and DFT (Design for Test) teams to address design challenges and ensure integration of all design components.