Senior Physical Design Engineer

NextSilicon is looking for a talented and experienced engineer to participate in the physical design activities of the company’s product. This position involves working with external back-end vendors as well as carrying out critical tasks in house, and leading aggressive back-end methods to meet challenging targets in terms of area, timing, and layout. In this role, you will be at the center of the company’s design efforts and will have a significant influence on product architecture.

Key qualifications

  • 10+ years of physical design experience, leading complex process designs
  • In-depth knowledge of process considerations and circuit aspects
  • Knowledge of physical design industry standards and practices, including physically aware synthesis, floor planning, and place and route
  • Experience developing and implementing power-grid and clock specifications
  • Solid understanding of all aspects of physical construction, integration, and physical verification
  • Good command of industry-standard physical design and synthesis tools
  • Understanding of scripting languages such as Perl and Tcl
  • Working knowledge of extraction and STA methodologies and tools
  • Good understanding of physical design verification methodology for debugging LVS and DRC issues at chip and block level
  • Proficiency in power delivery, signal integrity, advanced packaging, power projection, and design for low dynamic power
  • Master’s degree in electrical engineering or computer science, and/or equivalent experience


  • Generate and analyze critical block- and chip-level static timing constraints
  • Spec and define full chip floor plan, including pin placement, partitions, and power grid
  • Develop and validate high-performance, low-power clock network guidelines
  • Perform critical block-level place and route and make design decisions that meet timing, area, and power constraints
  • Review the vendors’ physical design verification flow at chip and block level and provide guidelines to other designers on how to fix LVS and DRC violations
  • Work with vendors on defining physical design methodologies and assist in flow development for chip integration