Senior Verification Engineer

NextSilicon is looking for a talented and experienced engineer to take part in the verification efforts for the company’s core product. This position involves building a complex verification environment from scratch, and defining and executing a test plan. In this role, you will be leading verification from A to Z and will have a critical impact on the company.

• 6+ years of verification experience, including hands-on experience building complex environments from scratch
• Advanced knowledge of verification flow and CPU and SOC architecture and design
• Expertise in verification languages such as SystemVerilog, UVM, OVM, Specman
• Knowledge of industry standard tools, including Verilog, Verilog simulator, and debug
• Clear understanding of constrained random verification process, functional coverage, code coverage, and assertion methodology and philosophy
• Experience with PCIe and DDR interfaces, Perl, Tcl, shell scripting, and Makefiles an advantage
• Master’s degree in electrical engineering or computer science, or equivalent experience

• Build and maintain a smart and scalable verification environment that ties into various systems (SW stack, FPGA, and ASIC RTL)
• Work with the software, design, and micro-architecture teams to understand the functional and performance goals of the product’s design
• Review specifications and develop attributes, tests, and coverage plans
• Define methodology and test benches
• Work closely with the verification team to ensure the quality of the product